FIG. 6 illustrates a prior-art example of the layout of a single-chip microcomputer circuit in which a CPU and a plurality of flash ROMs are placed on a chip. Specifically, the circuit has a CPU 1, a plurality of flash ROM macros 2-1 to 2-4 for storing programs, and an interleave controller 3 for exercising control when a fetch bus is interleaved.
The CPU 1 and interleave controller 3 run on an externally applied system clock. The latter is supplied via a clock tree deployed on the chip. Clock skew of the clock supplied to each of the circuit devices by the clock tree is held within a certain limits.
The flash ROMs 2-1 to 2-4 operate at a speed lower than the operating speed of, e.g., the CPU 1. In order to raise the operating speed of a single-chip microcomputer, therefore, the usual practice is to adopt an interleave configuration and operate the plurality of flash ROMs 2-1 to 2-4 alternately, whereby an apparent operating speed equivalent to that of the CPU 1 can be obtained. Clocks obtained by frequency-dividing the system clock in the interleave controller 3 are used as read clocks supplied to the flash ROMs 2-1 to 2-4 at this time.
FIG. 7 is a block diagram illustrating the structure of a conventional single-chip microcomputer circuit in a case where the circuit has two flash ROMs 2-1 and 2-2, the former on an odd-numbered side and the latter on an even-numbered side.
The CPU 1 is connected to the flash ROMs 2-1 and 2-2 via the interleave controller 3. In the connection between the CPU 1 and the interleave controller 3, the CPU 1 outputs addresses for fetching programs that have been stored in the flash ROMs 2-1 and 2-2 and for accessing data, a control signal for controlling the status of the fetch bus and a control signal for controlling clock status and generating a clock. These addresses and signals are output to the interleave controller 3. At the time of consecutive access, data that has been read out of the flash ROM 2-1 on the odd-numbered side and the flash OM 2-2 on the even-numbered side is output as a data signal from the interleave controller 3 to the CPU 1 while the interleave controller 3 switches between these items of data alternately.
In the connections between the interleave controller 3 and the flash ROMs 2-1 and 2-2, addresses that have been reconstructed within the interleave controller 3 in accordance with the flash ROM 2-1 on the odd-numbered side and the flash ROM 2-2 on the even-numbered side based upon the address data from the CPU 1 are output to the flash ROM 2-1 on the odd-numbered side and the flash ROM 2-2 on the even-numbered side, respectively. Further, the interleave controller 3 generates and supplies the read clocks for both the flash ROM 2-1 on the odd-numbered side and the flash ROM 2-2 on the even-numbered side. Data that has been read out of the flash ROMs 2-1 and 2-2 in sync with the read clocks from the interleave controller 3 are output from the flash ROMs 2-1 and 2-2 to the interleave controller 3.
FIG. 8 is a block diagram illustrating the structure of a conventional single-chip microcomputer circuit in a case where two sets of flash ROMs are adopted to conform to the layout of FIG. 6. This arrangement is similar to that of FIG. 7 except for the fact that two sets of flash ROMs (2-1 to 2-4) are disposed on the chip.
In these conventional circuit arrangements, the interleave controller 3 runs on a system clock whose frequency is the same as that of the CPU 1 using the control signal from the CPU 1. It is required, therefore, that set-up time and hold time of the signals be satisfied between the CPU 1 and interleave controller 3. As an operating frequency rises, however, the margin for set-up time diminishes. In a case where operating frequency is raised, therefore, the interleave controller 3 is placed close to the CPU 1. The interleave controller 3 provides address signals, which are reconstructed using the control signal from the CPU 1, generates the read clocks and supplies the address signals and read clocks to the flash ROMs 2-1 to 2-4.
Since the flash ROMs 2-1 to 2-4 occupy a large area, there is a limitation with regard to their positioning on the chip. In addition, the clock-input pins of each of the flash ROMs 2-1 to 2-4 are limited to a single location. After the placement of the flash ROMs 2-1 to 2-4 on the chip is decided, therefore, wiring is performed in such a manner that the read clocks from the interleave controller 3 to the flash ROMs 2-1 to 2-4 will be supplied directly to the flash ROMs over the shortest path. Thus it is so arranged that read-clock skew of each of the flash ROMs 2-1 to 2-4 will be held within fixed limits.
Other signals to be connected are also wired so as to avoid roundabout paths, thereby evening out skew.
FIG. 9 is a time chart illustrating the status of a conventional single-chip microcomputer at the time of a continuous fetch operation. The operation of this prior-art example will be described with reference to FIGS. 6 to 9.
A clock tree extends through a single-chip microcomputer and serves to hold skew between the clocks of a system clock (a) to within fixed limits.
Using the system clock (a), the interleave controller 3 generates both a read clock (d) for flash ROMs 2-2, 2-4 on the even side and a read clock (g) for flash ROMs 2-1, 2-3 on the odd side. These clocks are supplied to the flash ROMs over the shortest distances. Though wiring is implemented over the shortest distances, wiring of a certain length is nevertheless required from the interleave controller 3 to the flash ROMs 2-1 to 2-4. As a consequence, by the time the read clocks from the interleave controller 3 arrive at the clock input pins of the flash ROMs 2-1 to 2-4, they sustain a delay (referred to as “wiring delay”) ascribable to wiring length, as illustrated in FIG. 9.
Further, though read-out of data from the flash ROMs 2-1 to 2-4 starts in sync with the rising edges of the read clocks input to the flash ROMs 2-1 to 2-4, there is a large output delay with regard to the flash ROMs 2-1 to 2-4, as depicted in FIG. 9. Consequently, the moment at which read-out data Dn of address An designated by clock cycle (1) is finalized slides to clock cycle (2), as a result of which a further delay (wiring delay) ascribable to wiring length is inflicted upon signals from the output ends of the flash ROMs 2-1 to 2-4 to the CPU 1.
Accordingly, on the side of CPU 1, operation is so adapted that data at the address designated in clock cycle (I) is sampled at the rising edge of clock cycle (3) and data at the address designated in clock cycle (2) is sampled at the rising edge of clock cycle (4), as shown in FIG. 9. If the cycle of the system clock shortens, however, it becomes difficult to assure set-up time at the sampling points of the CPU 1 on these occasions as well.